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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. 2001 mos integrated circuit pd3728dz 7300 pixels 3 color ccd linear image sensor data sheet document no. s15417ej3v0ds00 (3rd edition) date published february 2006 ns cp (n) printed in japan the mark data sheet s15417ej3v0ds 2 pd3728dz block diagram 8 13 14 5 3 1 36 34 32 30 29 23 28 16 24 22 21 15 clb 1l gnd 20 2 1 (blue) tg1 (blue) tg2 (green) tg3 (red) v out 2 (blue, even) v out 1 (blue, odd) v out 3 (green, odd) v out 4 (green, even) v out 6 (red, even) v out 5 (red, odd) 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . photocell transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s1 s2 s7299 s7300 d129 d134 (green) photocell transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s1 s2 s7299 s7300 d129 d134 (red) photocell transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s1 s2 s7299 s7300 d129 d134 rb ?? 6 4 2 35 33 31 gnd gnd gnd gnd gnd gnd 9 10 7 v od data sheet s15417ej3v0ds 3 pd3728dz pin configuration (top view) ccd linear image sensor 36-pin ceramic dip (cerdip) (15.24 mm (600)) ? pd3728dz-az caution connect the no c onnection pins (nc) to gnd. photocell structure diagram photocell array structure diagram (line spacing) red green blue 1 1 1 7300 7300 7300 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 v out 4 gnd v out 6 gnd v out 5 gnd v od rb 10 nc nc nc 1 2 tg3 gnd nc nc output signal 4 (green, even) ground output signal 6 (red, even) ground output signal 5 (red, odd) ground output drain voltage reset gate clock shift register clock 10 no connection no connection no connection shift register clock 1 shift register clock 2 transfer gate clock 3 (for red) ground no connection no connection output signal 3 (green, odd) ground output signal 1 (blue, odd) ground output signal 2 (blue, even) ground reset feed-through level clamp clock last stage shift register clock 1 shift register clock 20 no connection no connection no connection shift register clock 2 shift register clock 1 transfer gate clock 1 (for blue) transfer gate clock 2 (for green) no connection no connection v out 3 gnd v out 1 gnd v out 2 gnd clb 1l 20 nc nc nc 2 1 tg1 tg2 nc nc 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 10 m m 3 m 7 channel stopper aluminum shield blue photocell array 10 m 10 m 10 m green photocell array red photocell array 4 lines (40 m) 4 lines (40 m) data sheet s15417ej3v0ds 4 pd3728dz absolute maximum ratings (t a = + 25 c) parameter symbol ratings unit output drain voltage v od ? 0.3 to + 15 v shift register clock voltage v 1 , v 1l , v 10 , v 2 , v 20 ? 0.3 to + 8 v reset gate clock voltage v rb ? 0.3 to + 8 v reset feed-through level clamp clock voltage v clb ? 0.3 to + 8 v transfer gate clock voltage v tg1 to v tg3 ? 0.3 to + 8 v operating ambient temperature note t a ? 25 to + 60 c storage temperature t stg ? 40 to + 100 c note use at the condition wi thout dew condensation. caution product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefor e the product must be used under conditions that ensure that the absolute maxi mum ratings are not exceeded. recommended operating conditions (t a = + 25 c) parameter symbol min. typ. max. unit output drain voltage v od 11.4 12.0 12.6 v shift register clock high level v 1h , v 1lh , v 10h , v 2h , v 20h 4.5 5.0 5.5 v shift register clock low level v 1l , v 1ll , v 10l , v 2l , v 20l ? 0.3 0 + 0.5 v reset gate clock high level v rbh 4.5 5.0 5.5 v reset gate clock low level v rbl ? 0.3 0 + 0.5 v reset feed-through level clamp clock high level v clbh 4.5 5.0 5.5 v reset feed-through level clamp clock low level v clbl ? 0.3 0 + 0.5 v transfer gate clock high level v tg1h to v tg3h 4.5 v 1h note v 1h note v (v 10h ) (v 10h ) transfer gate clock low level v tg1l to v tg3l ? 0.3 0 + 0.5 v data rate 2f rb ? 2 40 mhz note when transfer gate clock high level (v tg1h to v tg3h ) is higher than shift register clock high level (v 1h (v 10h )), image lag can increase. remark pin 9 ( 10) and pin 28 ( 20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate under 24 mhz or so. data sheet s15417ej3v0ds 5 pd3728dz electrical characteristics t a = + 25 c, v od = 12 v, f rb = 1 mhz, data rate = 2 mhz, storage time = 10 ms, input signal clock = 5 v p-p , light source: 3200 k halogen lamp + c-500s (infrared cut filter, t = 1 mm) +ha-50 (heat absorbin g filter, t = 3 mm) parameter symbol test conditions min. typ. max. unit saturation voltage v sat 1.5 2.0 ? v saturation exposure red ser ? 0.35 ? lxs green seg ? 0.39 ? lxs blue seb ? 0.31 ? lxs photo response non-uniformity prnu v out = 1.0 v ? 6.0 18.0 % average dark signal note1 ads1 light shielding ? 1.0 5.0 mv ads2 ? 0.5 5.0 mv dark signal non-uniformity note1 dsnu1 light shielding ? 2.0 5.0 mv dsnu2 ? 1.0 5.0 mv power consumption p w ? 600 800 mw output impedance z o ? 0.3 0.5 k ? response red r r 3.9 5.6 7.3 v/lxs green r g 3.6 5.1 6.6 v/lxs blue r b 4.5 6.4 8.3 v/lxs image lag note1 il1 v out = 1.0 v ? 2.0 5.0 % il2 ? 1.0 5.0 % offset level note2 v os 4.0 5.0 6.0 v output fall delay time note3 t d v out = 1.0 v ? 20 ? ns register imbalance ri v out = 1.0 v 0 ? 4.0 % total transfer efficiency tte v out = 1.0 v, data rate = 40 mhz 95 98 ? % response peak red ? 630 ? nm green ? 540 ? nm blue ? 460 ? nm dynamic range note1 dr11 v sat /dsnu1 ? 1000 ? times dr12 v sat /dsnu2 ? 2000 ? times dr21 v sat / bit1 ? 2000 ? times dr22 v sat / bit2 ? 4000 ? times reset feed-through noise note2 rftn light shielding ? 500 + 200 + 500 mv random noise note1 bit1 light shielding, ? 1.0 ? mv bit2 bit clamp mode (t cp = 150 ns) ? 0.5 ? mv line1 light shielding, ? 4.0 ? mv line2 line clamp mode (t19 = 3 s) ? 2.0 ? mv notes 1. ads1, dsnu1, il1, dr11, dr21, bit1 and line1 show the specification of v out 1 and v out 2. ads2, dsnu2, il2, dr12, dr22, bit2 and line2 show the specification of v out 3 to v out 6. 2. refer to timing chart 2, 5 . 3. when the fall time of 1l (t2?) is the typ. value (refer to timing chart 2, 5 ). data sheet s15417ej3v0ds 6 pd3728dz input pin capacitance (t a = + 25 c, v od = 12 v) parameter symbol pin name pin no. min. typ. max. unit shift register clock pin capacitance 1 c 1 1 13 ? 350 500 pf 23 ? 350 500 pf 10 9 ? 350 500 pf shift register clock pin capacitance 2 c 2 2 14 ? 350 500 pf 24 ? 350 500 pf 20 28 ? 350 500 pf last stage shift register clock pin capacitance c l 1l 29 ? 10 ? pf reset gate clock pin capacitance c rb rb 8 ? 10 ? pf reset feed-through level clamp clock pin capacitance c clb clb 30 ? 10 ? pf transfer gate clock pin capacitance c tg tg1 22 ? 100 ? pf tg2 21 ? 100 ? pf tg3 15 ? 100 ? pf remark pins 13, 23 ( 1) and pin 9 ( 10) are connected each other inside of the device. pins 14, 24 ( 2) and pin 28 ( 20) are connected each other inside of the device. data sheet s15417ej3v0ds 7 pd3728dz 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 120 122 124 126 128 130 132 7426 7428 7430 7432 7434 7436 7438 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 119 121 123 125 127 129 131 7425 7427 7429 7431 7433 7435 7437 v out 1, 3, 5 v out 2, 4, 6 note invalid photocell (6 pixels) invaid photocell (6 pixels) valid photocell (7300 pixels) optical black (96 pixels) note rb clb 10) 1 ( 1l 20) 2 ( tg1 to tg3 timing chart 1 (bit clamp mode, for each color) note input the rb and clb pulses continuously during this period, too. data sheet s15417ej3v0ds 8 pd3728dz timing chart 2 (bit clamp mode, for each color) symbol min. typ. max. unit t1, t2 0 50 ? ns t1?, t2? 0 5 ? ns t3 17 50 ? ns t4 5 200 ? ns t5, t6 0 20 ? ns t7 17 150 ? ns t8, t9 0 20 ? ns t10 ? 10 note 1 + 50 ? ns t11 ? 5 note 2 + 50 ? ns t cp 5 150 ? ns notes 1. min. of t10 shows that the rb and clb overlap each other. 2. min. of t11 shows that the 1l and clb overlap each other. rb clb 90% 90% t10 1l clb 90% 90% t11 90% t10 t1' t5 t6 t4 t3 t2' t d v os rftn 10% t11 t9 t8 t cp t7 t1 t2 90% 10% 90% 10% 10% 90% 10% 90% 10% v out 1 to v out 6 rb clb 10) 1 ( 1l 20) 2 ( data sheet s15417ej3v0ds 9 pd3728dz timing chart 3 (bit clamp, for each color) symbol min. typ. max. unit t11 ? 5 note 2 + 50 ? ns t12 3000 10000 ? ns t13, t14 0 50 ? ns t15, t16 900 1000 ? ns notes 1. input the rb and clb pulses continuously during this period, too. 2. min. of t11 shows that the 1l and clb overlap each other. t12 t14 t13 90% 10% t15 90% 90% t11 90% note1 t16 rb clb 10) 1 ( 1l 20) 2 ( tg1 to tg3 1l clb 90% 90% t11 data sheet s15417ej3v0ds 10 pd3728dz 1, 2 and 10, 20 cross points 1 2 2 v or more 2 v or more 10 20 2 v or more 2 v or more 1l, 20 cross points 20 1l 2 v or more 0.5 v or more remark adjust cross points ( 1, 2), ( 10, 20) and ( 1l, 20) with input resistance of each pin. data sheet s15417ej3v0ds 11 pd3728dz 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 120 122 124 126 128 130 132 7426 7428 7430 7432 7434 7436 7438 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 119 121 123 125 127 129 131 7425 7427 7429 7431 7433 7435 7437 v out 1, 3, 5 v out 2, 4, 6 rb clb 10) note invalid photocell (6 pixels) invalid photocell (6 pixels) valid photocell (7300 pixels) optical black (96 pixels) 1 ( 1l 20) 2 ( tg1- tg3 note note set the rb pulse to high level during this period. remark inverse pulse of tg1 to tg3 can be used as clb. timing chart 4 (line clamp mode, for each color) data sheet s15417ej3v0ds 12 pd3728dz timing chart 5 (line clamp mode, for each color) symbol min. typ. max. unit t1, t2 0 50 ? ns t1?, t2? 0 5 ? ns t3 17 50 ? ns t4 5 200 ? ns t5, t6 5 20 ? ns "h" t1' t5 t6 t4 t3 t2' t d v os rftn 10% t1 t2 90% 10% 90% 10% 90% 10% 90% 10% v out 1 to v out 6 rb clb 10) 1 ( 1l 20) 2 ( data sheet s15417ej3v0ds 13 pd3728dz timing chart 6 (line clamp mode, for each color) symbol min. typ. max. unit t12 3000 10000 ? ns t13, t14 0 50 ? ns t15, t16 900 1000 ? ns t17, t18 100 1000 ? ns t19 200 t12 ? ns t20, t21 0 20 ? ns note set the rb pulse to high level during this period. remark inverse pulse of the tg1 and tg3 can be used as clb. 1, 2, and 10, 20 cross points 1 2 2 v or more 2 v or more 10 20 2 v or more 2 v or more 1l, 20 cross points 20 1l 2 v or more 0.5 v or more remark adjust cross points ( 1, 2), ( 10, 20) and ( 1l, 20) with input resistance of each pin. t12 t14 t13 90% 10% 90% 10% t15 t20 t21 t18 t17 90% 90% t19 note t16 rb clb 10) 1 ( 1l 20) 2 ( tg1 to tg3 data sheet s15417ej3v0ds 14 pd3728dz definitions of characteristic items 1. saturation voltage : v sat output signal voltage at whic h the response linearity is lost. 2. saturation exposure : se product of intensity of illumination (lx) and storag e time (s) when saturation of output voltage occurs. 3. photo response non-uniformity : prnu the output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. this is calculated by the following formula. 4. average dark signal : ads average output signal voltage of all the va lid pixels at light shielding. this is calculated by the following formula. prnu (%) = x = x j : output voltage of valid pixel number j x x : maximum of ? x j ? x ? x 7300 j = 1 7300 x j 100 ? ? x register dark dc level v out x ? ads (mv) = d j : dark signal of valid pixel number j 7300 j = 1 7300 d j data sheet s15417ej3v0ds 15 pd3728dz 5. dark signal non-uniformity : dsnu absolute maximum of the difference between ads and vo ltage of the highest or lowest output pixel of all the valid pixels at light shielding. this is calculated by the following formula. 6. output impedance : z o impedance of the output pins viewed from outside. 7. response : r output voltage divided by exposure (lxs). note that the response varies with a light source (spectral characteristic). 8. image lag : il the rate between the last output voltage and the next one after read out the data of a line. d j : dark signal of valid pixel number j dsnu (mv) : maximum of ? d j ? ads ? j = 1 to 7300 ads dsnu register dark dc level v out v out tg light v out on off v 1 il (%) = v 1 v out 100 data sheet s15417ej3v0ds 16 pd3728dz 9. register imbalance : ri the rate of the difference betwe en the averages of the out put voltage of odd and even pixels, against the average output voltage of all the valid pixels. this is calculated by the following formula. 10. total transfer efficiency : tte the total transfer rate of ccd analog shift register. this is calculated by the following formula, it is defined by each output. tte (%) = (1 ? v b / average output of all the valid pixels) 100 v a ? 1 : the last pixel output ? 1 (odd pixel: 7431st pixel) v a : the last pixel output (odd pixel: 7433rd pixel) v b : the spilt pixel output (odd pixel: 7435th pixel) v a ? 1 v a v b 11. random noise : random noise is defined as the stan dard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). this is calculated by the following formula. this is measured by the dc level sampling of only the signal level, not by cds (correlated double sampling). ri (%) = 2 n j = 1 j = 1 n 2 (v 2j ?1 ? v 2j ) 1 n n v j 100 n v j : number of valid pixels : output voltage of each pixel (mv) = , v = i = 1 100 (v i ? v) 2 i = 1 100 v i 100 100 1 v i : a valid pixel output signal among all of the valid pixels for each color v 1 v 100 v 2 line 2 line 100 line 1 v out data sheet s15417ej3v0ds 17 pd3728dz standard characteristic curves (reference value) dark output temperature characteristic storage time output voltage characteristic (t a = +25 c) operating ambient temperature t a ( c) storage time (ms) 8 4 2 1 0.5 0.25 0.1 10 0 20304050 relative output voltage relative output voltage 2 1 0.2 0.1 1510 100 b b g g r 80 60 40 20 0 400 500 600 700 800 wavelength (nm) response ratio (%) total spectral response characteristics (without infrared cut filter and heat absorbing filter) (t a = +25 c) data sheet s15417ej3v0ds 18 pd3728dz application circuit example caution connect the no connection pins (nc) to gnd. v out 3 gnd v out 4 v out 1 v out 6 v out 2 v out 5 gnd gnd gnd gnd v od rb nc gnd clb nc nc nc nc 2 nc 1 2 gnd nc nc 1 tg1 nc nc tg2 tg3 10 20 1l pd3728dz + + + + 5 v + 12 v + 5 v b4 b6 b5 b1 b3 b2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 47 ? 10 ? 47 ? 2 ? 2 ? 2 ? 2 ? 2 ? 2 ? 47 ? 2 ? 2 ? 2 ? 1 tg clb rb 2 0.1 f 47 f/25 v 0.1 f 10 f/16 v 0.1 f 10 f/16 v data sheet s15417ej3v0ds 19 pd3728dz remarks 1. pin 9 ( 10) and pin 28 ( 20) should be open to decrease the infl uence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate under 24 mhz or so. 2. inverters shown in the above application circuit example are the 74ac04. 3. b1 to b6 in the application circuit example are shown in the figure below. b1-b6 equivalent circuit ccd v out 47 f/25 v 0.1 f + +12 v 110 ? 2sc945 1 k ? 4.7 k ? 47 ? 2sa1005 data sheet s15417ej3v0ds 20 pd3728dz package drawing ccd linear image sensor 36-pin ceramic dip (15.24 mm (600)) 3.00 0.08 11.00 0.15 3.4 0.3 (2.6) (2.8) 0.25 0.05 1.00 (6.00) 2.8 0.08 4.85 0.38 1.00 0.2 4.00 0.2 20.32 0.13 (17.09 max.) (15.24 min.) 48.26 0.4 0.46 0.05 24.13 0.2 20.32 0.13 1.27 2.54 13.00 0.5 14.66 1.00 0.08 the 1st valid pixel index mark 46.00 0.5 94.00 0.7 35.00 0.6 name dimensions refractive index glass cap 1.5 36d-1ccd-pkg2-4 93.0 9.0 1.1 1 1st valid pixel center of package 2 the bottom of package the surface of the chip 3 the surface of the chip the surface of the glass cap 4 the tolerance of package dimension 0.25 : less than 10mm from w/f edge 0.50 : equal or more than 10mm from w/f edge 2 3 4 1 data sheet s15417ej3v0ds 21 pd3728dz recommended soldering conditions when soldering this product, it is highly recommended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. type of through-hole device pd3728dz-az : ccd linear image sensor 36-pi n ceramic dip (cerdip) (15.24 mm (600)) process conditions partial heating method pin temperature : 300 c or below, heat time : 3 seconds or less (per pin) cautions 1. during assembly care should be taken to prevent solder or fl ux from contacting the glass cap. the optical characteristics could be degraded by such contact. 2. soldering by the solder flow method ma y have deleterious effects on prevention of glass cap soiling and heat resistance. so the method cannot be guaranteed. data sheet s15417ej3v0ds 22 pd3728dz notes on handling the packages mounting of the package glass cap the application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. particular care should be taken when mounting the package on the circuit board. don't have any object come in contact with glass cap. you should not reform the lead frame. we recommended to use a ic-inserter when you assemble to pcb. also, be care that the any of the following can cause the package to crack or dust to be generated. 1. applying heat to the external leads for an extended period of time with soldering iron. 2. applying repetitive bending stress to the external leads. 3. rapid cooling or heating for this product, the reference value for the three-point bending strength note is 180 [n] (at distance between supports: 70 mm). avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic). note three-point bending strength test distance between supports: 70 mm, support r: r 2 mm, loading rate: 0.5 mm/min. don?t either touch glass cap surface by hand or have any object come in contact with glass cap surface. care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. for dirt stuck through electricity ionized air is recommended. 1 2 70 mm load load 70 mm data sheet s15417ej3v0ds 23 pd3728dz notes on handling the packages operate and storage environments 3 operate in clean environments. ccd image sensors are precise optical equipment that should not be subject to mechanical shocks. exposure to high temperatures or humidity will affect the characteristics. so avoid storage or usage in such conditions. keep in a case to protect from dust and dirt. dew condensation may occur on ccd image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. avoid such rapid temperature changes. for more details, refer to our document "review of quality and reliability handbook" (c12769e) electrostatic breakdown ccd image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. before handling be sure to take the following protective measures. 1. ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. either handle bare handed or use non-chargeable gloves, clothes or material. 4. ionized air is recommended for discharge when handling ccd image sensor. 5. for the shipment of mounted substrates, use box treated for prevention of static charges. 6. anyone who is handling ccd image sensors, mounting them on pcbs or testing or inspecting pcbs on which ccd image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 m ? . 4 data sheet s15417ej3v0ds 24 pd3728dz [ memo ] data sheet s15417ej3v0ds 25 pd3728dz [ memo ] data sheet s15417ej3v0ds 26 pd3728dz [ memo ] data sheet s15417ej3v0ds 27 pd3728dz 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 pd3728dz the information in this document is current as of february, 2006. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec e lectronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": |
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